UCAgent: An End-to-End Agent for Block-Level Functional Verification
Summary: arXiv:2603.25768v1 Announce Type: cross
Abstract
Functional verification remains a critical bottleneck in modern integrated circuit (IC) development cycles, accounting for approximately 70% of total development time in many projects. However, traditional methods, including constrained-random and formal verification, struggle to keep pace with the growing complexity of modern semiconductor designs.
While recent advances in Large Language Models (LLMs) have shown promise in code generation and task automation, significant challenges hinder the realization of end-to-end functional verification automation. These challenges include:
- Limited accuracy in generating Verilog/SystemVerilog verification code.
- The fragility of LLMs when executing complex, multi-step verification workflows.
- The difficulty of maintaining verification consistency across specifications, coverage models, and test cases throughout the workflow.
Proposed Solution: UCAgent
To address these challenges, we propose UCAgent, an end-to-end agent that automates hardware block-level functional verification based on three core mechanisms:
- Pure Python Verification Environment: We establish a pure Python verification environment using Picker and Toffee to avoid reliance on LLM-generated SystemVerilog verification code.
- Configurable 31-Stage Verification Workflow: We introduce a configurable 31-stage fine-grained verification workflow to guide the LLM, where each stage is verified by an automated checker.
- Verification Consistency Labeling Mechanism (VCLM): This mechanism assigns hierarchical labels to LLM-generated artifacts, thereby improving the reliability and traceability of verification.
Experimental Results
Experimental results show that UCAgent can complete end-to-end automated verification on multiple modules, including the UART, FPU, and integer divider modules. UCAgent achieves:
- Up to 98.5% code coverage.
- Up to 100% functional coverage.
- Discovery of previously unidentified design defects in realistic designs, demonstrating its practical potential.
Conclusion
The advent of UCAgent marks a significant step forward in the field of functional verification. By automating the verification process and addressing the inherent challenges of traditional methods, UCAgent offers a promising solution to enhance the efficiency and effectiveness of IC development cycles. This innovation not only reduces the time spent on verification but also improves the reliability of semiconductor designs, ultimately paving the way for more complex and capable electronic systems.