HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
The landscape of Integrated Circuit (IC) verification is undergoing a significant transformation with the introduction of HAVEN (Hybrid Automated Verification ENgine), a novel framework designed to enhance the efficiency of testbench synthesis using Large Language Models (LLMs). As integrated circuit verification accounts for nearly 70% of the IC development cycle, the demand for automated solutions has never been higher.
Despite the promising capabilities of LLMs in generating code, challenges remain, particularly when it comes to Hardware Description Languages (HDLs). These languages are not well-represented in LLM training datasets, often resulting in incorrect or inefficient code generation. To address these issues, HAVEN employs a hybrid approach that combines the analytical strengths of LLMs with a structured framework for generating Universal Verification Methodology (UVM) testbenches and sequences.
Key Features of HAVEN
- Architectural Planning: HAVEN utilizes LLM agents to analyze design specifications and produce a structured architectural plan, ensuring that the generated testbenches are both comprehensive and aligned with design requirements.
- Template Engine: The HAVEN Template Engine integrates predefined and protocol-specific templates to generate UVM components. This approach guarantees correct bus-handshake timing, which is critical for the reliability of the testbench.
- Protocol-Aware DSL: For UVM sequence generation, HAVEN introduces a Protocol-Aware Sequence Domain-Specific Language (DSL) that breaks down sequences into fine-grained step types, enhancing the granularity and precision of the generated sequences.
- Coverage Optimization: The framework includes a mechanism for iteratively improving coverage rates by analyzing coverage gap reports. LLMs are leveraged to compose additional targeted DSL sequences, thereby enhancing the overall testbench quality.
Performance Metrics
In experimental evaluations conducted on 19 open-source IP designs across three distinct interface protocols—Direct, Wishbone, and AXI4-Lite—HAVEN has demonstrated impressive performance metrics:
- Compilation Success: 100% compilation success rate, indicating that all generated testbenches compile without errors.
- Code Coverage: An average code coverage of 90.6%, showcasing the thoroughness of the generated testbenches in exercising the design.
- Functional Coverage: Achieving an average functional coverage of 87.9%, which reflects the effectiveness of the testbenches in validating the intended functionality of the designs.
Conclusion
HAVEN stands out as a significant advancement in the realm of LLM-assisted testbench generation systems. By addressing the limitations of traditional LLMs in generating HDLs and offering a structured framework that incorporates protocol-specific templates and a robust DSL, HAVEN not only improves efficiency but also enhances the reliability of the verification process. Its state-of-the-art performance metrics underscore its potential to redefine the standards of IC verification, making it an essential tool for engineers and developers in the field.
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