DiagramNet: An End-to-End Recognition Framework and Dataset for Non-Standard System-Level Diagrams
Recent advancements in artificial intelligence have opened new frontiers in recognizing and interpreting complex system-level diagrams that are crucial for chip design. A new paper titled “DiagramNet,” recently released on arXiv (2605.01338v1), introduces a pioneering multimodal dataset aimed at tackling the challenges faced by existing multimodal large language models (MLLMs) in this domain.
System-level diagrams serve as the architectural blueprint for chip design, detailing essential elements such as module functions, dataflows, and interface protocols. Despite their importance, challenges arise due to the non-standardized symbols used in these diagrams and the lack of structured training data, which significantly impede the efficacy of current MLLMs. DiagramNet addresses these issues by providing a comprehensive dataset and a novel framework for improved diagram recognition.
Key Features of DiagramNet
- Dataset Composition: The Dataset includes 10,977 connection annotations and 15,515 chain-of-thought QA pairs tailored for four distinct tasks: Listing, Localization, Connection, and Circuit QA.
- Progressive Training Pipeline: The framework employs a progressive training pipeline that enhances the model’s learning capabilities by structuring the training process into manageable phases.
- Decoupled Multi-Agent Workflow: This innovative approach breaks down complex visual reasoning into three distinct stages: Perception, Reasoning, and Knowledge, facilitating more effective learning and understanding.
Performance and Benchmarking
The performance of DiagramNet has been rigorously evaluated against existing models. The 3B-parameter model, integrated with the proposed workflow, has demonstrated remarkable results, surpassing the 2025 EDA Elite Challenge winner. Additionally, it outperformed notable models such as GPT-5, Claude-Sonnet-4, and Gemini-2.5-Pro by more than two times in end-to-end evaluations.
One of the standout features of this framework is its ability to generalize effectively across different models. For instance, it has significantly boosted Task 1 performance by impressive margins—128.7 times for Gemini-2.5-Pro and 12.4 times for GPT-5. Such enhancements indicate that the workflow not only benefits the original model but also extends its advantages to other systems.
Transfer Learning and Zero-Shot Reasoning
Another critical aspect of DiagramNet is its efficiency in transfer learning. With only 60 images utilized for detector adaptation, the method has shown effective transfer capabilities to the AMSBench dataset. This approach has enabled zero-shot connectivity reasoning that matches the performance of advanced models like GPT-5 and Claude-Sonnet-4, while simultaneously exceeding the capabilities of the current AMS state-of-the-art method, Netlistify.
Conclusion
DiagramNet represents a significant advancement in the field of AI-driven diagram recognition, providing both a robust dataset and an innovative framework capable of overcoming existing limitations in the analysis of non-standard system-level diagrams. As research in this area continues to evolve, DiagramNet stands as a testament to the potential of AI in enhancing the efficiency and accuracy of chip design processes.
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