From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
Summary: arXiv:2504.19959v3 Announce Type: cross
Abstract
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of the total development effort. While the Universal Verification Methodology (UVM) is widely used in industry to improve verification efficiency through structured and reusable testbenches, constructing these testbenches and generating sufficient stimuli remain challenging. These challenges arise from the considerable manual coding effort required, repetitive manual execution of multiple EDA tools, and the need for in-depth domain expertise to navigate complex designs.
The UVM^2 Framework
In response to these challenges, we present UVM2, an automated verification framework that leverages Large Language Models (LLMs) to generate UVM testbenches and iteratively refine them using coverage feedback. This innovative approach significantly reduces manual effort while maintaining rigorous verification standards.
Key Features of UVM^2
- Automation of Testbench Generation: UVM2 utilizes LLMs to automate the creation of testbenches, thereby minimizing the need for extensive manual coding.
- Iterative Refinement: The framework employs an iterative approach to refine testbenches based on coverage feedback, ensuring that the verification process is both efficient and effective.
- Expertise Reduction: By reducing the reliance on in-depth domain expertise, UVM2 opens up verification to a broader range of engineers, facilitating faster project timelines.
Benchmarking UVM^2
To evaluate the efficacy of UVM2, we introduced a benchmark suite comprising Register Transfer Level (RTL) designs of up to 1.6K lines of code. The results from this benchmarking exercise are promising:
- UVM2 reduces testbench setup time by up to 30% compared to experienced engineers.
- The framework achieves average code coverage of 87.44% and function coverage of 89.58%.
- UVM2 outperforms state-of-the-art solutions by 20.96% in code coverage and 23.51% in function coverage.
Conclusion
UVM2 represents a significant advancement in the field of IC verification, addressing longstanding challenges associated with manual testbench creation and execution. By harnessing the power of LLMs, UVM2 not only streamlines the verification process but also enhances the overall quality and reliability of IC designs. As the industry continues to evolve, frameworks like UVM2 will play a crucial role in driving innovation and efficiency in semiconductor development.